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Safety engineering efforts are normally worked
in unison with reliability engineering activities.
The reliability engineering activities include
FMECA and
RCM. These
analyses can be used to support various safety
engineering tasks. Listed are an examples of the
types of safety analyses which would use the
reliability engineering analysis. A safety
engineering program could be set up following
Mil-Std-882 System Safety Program Requirements.
- 1. Hazard Analysis
- 2. Fault Tree
- 3. Sneak Circuit Analysis
Hazard
Analysis
Hazard Analyses is a technique which by
qualitative or quantitative analysis is used to
identify hazards, their causes and effects. The
hazard elimination, or risk mitigation would be
documented in the hazard analysis. This analysis
can be conducted to identify hazard associated with
the system, subsystem, components, personnel,
ground support equipment, GFE, facilities, and take
into consideration their interrelationship and
impact with the logistic support, training,
maintenance, and operational environments.
Fault Tree
Analysis
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A Fault Tree Analysis, contrary to the
FMECA, is a top-down analysis. It takes on
a deductive approach defining the events
and sub-event, which may cause the top
event to occur. The relationship between
these events is governed by their logical
relationship to each other. The level that
the deductive approach could be taken down
to is a basic event. These basic events
can be the failure modes of components or
functions, as identified in the FMECA.
Other factors can also be taken into
consideration in the development of the
fault tree.
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The fault tree can be represented in a
qualitative or quantitative manner. The qualitative
would provide the illustrated or graphical
relationship of the top event and all of its
subordinate events and their basic events. Where as
the quantitative would also include "probability of
occurrence" of all events rolled up to the top
event. The probability of occurrence can be
expressed in Boolean algebra. Therefore the laws
apply where in some cases the Boolean expression
could be simplified. This would simplify the actual
calculation of the final end event.
The simplification of the whole Boolean algebra
expression would be important where, for example a
basic event (know failure mode) appeared in more
than one location (branches) in the fault tree. For
complex fault trees the use a dedicated software
program to build and run the calculations would be
warranted.
In constructing a fault tree special attention
must be made to the logical relationship between
the events. It could be easy to have two or more
events flowing into an OR gate when in fact the
gate should be an AND gate. This building of a
fault tree can be further complicated by a system's
redundant elements and characteristics.
Fault Tree Analysis
Symbols
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Top
Event: This symbol
represents the end event that is being
considered in the Fault tree Analysis
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Fault Event:
This block contains a
description of the logical result of lower
events
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House Event:
This represents a system
operation condition, that could in the
normal sequence of events cause a state
change in the logic.
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Basic event:
This represents a event at the
lowest level of the system under
examination. This event could be a failure
mode as identified in the Failure
Modes and Effects Criticality Analysis
(FMECA)
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Undeveloped
Event: This symbol represents a
condition that cannot or has yet to be
developed further
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Transfer
function: These symbols
"transfer out" and "transfer in" represent
a connection between two (or more) points
in the fault tree. This can be used to
minimize the duplication of an developed
branch in the fault tree.
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AND Gate:
An output will occur when all
inputs are present thus for a two input
gate A and B = output
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OR Gate:
An output will occur when
either one or all inputs are present, thus
for a two input gate A or B = output
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Ordered AND
Gate: Similar to the AND Gate,
but the inputs must occur in a specific
sequence.
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Sneak Circuit
Analysis
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